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1/12 september 2005 STP10NK50Z stf10nk50z n-channel 500v - 0.55 ? - 9a to-220 / to-220fp zener-protected supermesh?mosfet table 1: general features typical r ds (on) = 0.55 ? extremely high dv/dt capability 100% avalanche tested gate charge minimized very low intrinsic capacitances very good manufacturing repeatibility description the supermesh? series is obtained through an extreme optimization of st?s well established strip-based powermesh? layout. in addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. such series complements st full range of high voltage mos - fets including revolutionary mdmesh? products. applications high current, high speed switching ideal for off-line power supplies, adaptors and pfc lighting table 2: order codes figure 1: package figure 2: internal schematic diagram type v dss r ds(on) i d pw STP10NK50Z stf10nk50z 500 v 500 v < 0.7 ? < 0.7 ? 9 a 9 a(*) 125 w 30 w to-220 to-220fp 1 2 3 sales type marking package packaging STP10NK50Z p10nk50z to-220 tube stf10nk50z f10nk50z to-220fp tube rev. 2
STP10NK50Z - stf10nk50z 2/12 table 3: absolute maximum ratings ( ) pulse width limited by safe operating area (1) i sd 9 a, di/dt 200a/s, v dd 400 (*) limited only by maximum temperature allowed table 4: thermal data table 5: avalanche characteristics table 6: gate-source zener diode protection features of gate-to-source zener diodes the built-in back-to-back zener diodes have specifically been designed to enhance not only the device?s esd capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. in this respect the zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device?s integrity. these integrated zener diodes thus avoid the usage of external components. symbol parameter value unit to-220 to-220fp v ds drain-source voltage (v gs = 0) 500 v v dgr drain-gate voltage (r gs = 20 k ? ) 500 v v gs gate- source voltage 30 v i d drain current (continuous) at t c = 25c 9 9 (*) a i d drain current (continuous) at t c = 100c 5.7 5.7(*) a i dm ( ) drain current (pulsed) 36 36(*) a p tot total dissipation at t c = 25c 125 30 w derating factor 1 0.24 w/c v esd(g-s) gate source esd(hbm-c=100pf, r=1.5k ?) 4000 v dv/dt (1) peak diode recovery voltage slope 4.5 v/ns v iso insulation withstand voltage (dc) -- 2500 v t j t stg operating junction temperature storage temperature -55 to 150 c to-220 to-220fp rthj-case thermal resistance junction-case max 1 4.2 c/w rthj-amb thermal resistance junction-ambient max 62.5 c/w t l maximum lead temperature for soldering purpose 300 c symbol parameter max value unit i ar avalanche current, repetitive or not-repetitive (pulse width limited by t j max) 9 a e as single pulse avalanche energy (starting t j = 25 c, i d = i ar , v dd = 50 v) 230 mj symbol parameter test conditions min. typ. max. unit bv gso gate-source breakdown voltage igs= 1ma (open drain) 30 v
3/12 STP10NK50Z - stf10nk50z electrical characteristics (t case =25c unless otherwise specified) table 7: on/off table 8: dynamic table 9: source drain diode note: 1. pulsed: pulse duration = 300 s, duty cycle 1.5 %. 2. pulse width limited by safe operating area. 3. c oss eq. is defined as a constant equivalent capacitance giving the same charging time as c oss when v ds increases from 0 to 80% v dss . symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 1 ma, v gs = 0 500 v i dss zero gate voltage drain current (v gs = 0) v ds = max rating v ds = max rating, t c = 125 c 1 50 a a i gss gate-body leakage current (v ds = 0) v gs = 20 v 10 a v gs(th) gate threshold voltage v ds = v gs , i d = 100 a 3 3.75 4.5 v r ds(on) static drain-source on resistance v gs = 10 v, i d = 4.5 a 0.55 0.7 ? symbol parameter test conditions min. typ. max. unit g fs (1) forward transconductance v ds = 15 v , i d = 4.5 a 7 s c iss c oss c rss input capacitance output capacitance reverse transfer capacitance v ds = 25 v, f = 1 mhz, v gs = 0 1219 159 40 pf pf pf c oss eq. (3) equivalent output capacitance v gs = 0v, v ds = 0v to 400 v 806 pf t d(on) t r t d(off) t f turn-on delay time rise time turn-off delay time fall time v dd = 250 v, i d = 4.5 a r g = 4.7 ? v gs = 10 v (see figure 19) 19 17 43 15 ns ns ns ns q g q gs q gd total gate charge gate-source charge gate-drain charge v dd = 400 v, i d = 9 a, v gs = 10 v (see figure 22) 39.2 7.42 20.7 nc nc nc symbol parameter test conditions min. typ. max. unit i sd i sdm (2) source-drain current source-drain current (pulsed) 9 36 a a v sd (1) forward on voltage i sd = 9 a, v gs = 0 1.6 v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 9 a, di/dt = 100 a/s v dd = 35 v, t j = 25c (see figure 20) 268 1.83 13.7 ns c a t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 9 a, di/dt = 100 a/s v dd = 35 v, t j = 150c (see figure 20) 343 2.6 15.15 ns c a
STP10NK50Z - stf10nk50z 4/12 figure 3: safe operating area for to-220 figure 4: safe operating area for to-220fp figure 5: output characteristics figure 6: thermal impedance for to-220 figure 7: thermal impedance for to-220fp figure 8: transfer characteristics
5/12 STP10NK50Z - stf10nk50z figure 9: transconductance figure 10: gate charge vs gate-source voltage figure 11: normalized gate threshold voltage vs temperature figure 12: static drain-source on resistance figure 13: capacitance variations figure 14: normalized on resistance vs tem - perature
STP10NK50Z - stf10nk50z 6/12 figure 15: source-drain forward characteris - tics figure 16: maximum avalanche energy vs temperature figure 17: normalized bvdss vs temperature
7/12 STP10NK50Z - stf10nk50z figure 18: unclamped inductive load test cir - cuit figure 19: switching times test circuit for resistive load figure 20: test circuit for inductive load switching and diode recovery times figure 21: unclamped inductive wafeform figure 22: gate charge test circuit unclamped inductive load test circuit
STP10NK50Z - stf10nk50z 8/12 in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect . the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com
9/12 STP10NK50Z - stf10nk50z dim. mm. inch min. typ max. min. typ. max. a 4.40 4.60 0.173 0.181 b 0.61 0.88 0.024 0.034 b1 1.15 1.70 0.045 0.066 c 0.49 0.70 0.019 0.027 d 15.25 15.75 0.60 0.620 e 10 10.40 0.393 0.409 e 2.40 2.70 0.094 0.106 e1 4.95 5.15 0.194 0.202 f 1.23 1.32 0.048 0.052 h1 6.20 6.60 0.244 0.256 j1 2.40 2.72 0.094 0.107 l 13 14 0.511 0.551 l1 3.50 3.93 0.137 0.154 l20 16.40 0.645 l30 28.90 1.137 ?p 3.75 3.85 0.147 0.151 q 2.65 2.95 0.104 0.116 to-220 mechanical data
STP10NK50Z - stf10nk50z 10/12 l2 a b d e h g l6 f l3 g1 123 f2 f1 l7 l4 l5 dim. mm. inch min. typ max. min. typ. max. a 4.4 4.6 0.173 0.181 b 2.5 2.7 0.098 0.106 d 2.5 2.75 0.098 0.108 e 0.45 0.7 0.017 0.027 f 0.75 1 0.030 0.039 f1 1.15 1.7 0.045 0.067 f2 1.15 1.7 0.045 0.067 g 4.95 5.2 0.195 0.204 g1 2.4 2.7 0.094 0.106 h 10 10.4 0.393 0.409 l2 16 0.630 l3 28.6 30.6 1.126 1.204 l4 9.8 10.6 .0385 0.417 l5 2.9 3.6 0.114 0.141 l6 15.9 16.4 0.626 0.645 l7 9 9.3 0.354 0.366 ? 3 3.2 0.118 0.126 to-220fp mechanical data
11/12 STP10NK50Z - stf10nk50z table 10: revision history date revision description of changes 01-jul-2005 1 first release. 08-sep-2005 2 inserted ecopak indication
STP10NK50Z - stf10nk50z 12/12 i nformation furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the con sequence s o f use of such information nor for any infringement of patents or other rights of third parties which may result from its use. n o license is grante d b y implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicatio n are subjec t t o change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics produ cts are no t a uthorized for use as critical components in life support devices or systems without express written approval of stmicroelectron ics. the st logo is a registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2005 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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